1. Field of the Invention
The present invention relates to a successive approximated register analog-to-digital converter and a conversion method thereof, and more particularly, to a successive approximated register analog-to-digital converter and a conversion method thereof capable of improving performance while reducing power consumption.
2. Discussion of Related Art
Digital signal processing is more advantageous than analog signal processing due to its characteristics of high data processing speed and imperviousness to environmental noise. However, since most signals present in nature are in an analog form, it is necessary to convert an input analog signal to a digital signal in an integrated circuit.
Analog-to-digital converters may be generally classified into a pipeline analog-to-digital converter, a successive approximated register analog-to-digital converter, a flash analog-to-digital converter, and a delta-sigma analog-to-digital converter. The analog-to-digital converter has a suitable structure according to a sampling rate and a resolution.
Among these, the successive approximated register analog-to-digital converter has an advantage in that power consumption is much lower than that of analog-to-digital converters having different structures due to its high dependence on digital circuits. However, an output with a resolution of a certain level or higher in a conventional successive approximated register analog-to-digital converter is limited due to mismatch of an adjacent capacitor due to a change in a process of a capacitor digital-to-analog converter, and an insufficient resolution of the comparator.
Accordingly, recently, technology for improving a resolution of an analog-to-digital converter while using the same comparator has been actively studied. Examples of the technology include a majority voting scheme based on a theory of probability, an oversampling scheme for increasing a sampling rate to cause noise to be distributed over a wide band, resulting in low noise, and technology for intentionally continuously applying a specific pattern to a capacitor digital-to-analog converter to reduce noise. However, the majority voting scheme has a disadvantage in that a cycle of 5 clocks should be used in order to additionally obtain 1 bit, and the oversampling scheme has a disadvantage in that an input frequency band of an analog-to-digital converter is limited.
As the related art, there is Korean Patent Publication No. 10-1253224 (Title: Analog-to-digital Converter).